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engineering specification type 15.0 uxga color tft/lcd module model name:ITUX97C document control number : oem i-97c-02 note:specification is subject to change without notice. consequently it is better to contact to international display technology before proceeding with the design of your product incorporating this module. product development international display technology engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 1/31
i contents i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 interface signal connector 5.3 interface signal description 5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver 5.4.2 lvds receiver internal circuit 5.5 signal for lamp connector 6.0 pixel format image 7.0 parameter guide line for cfl inverter 8.0 interface timings 8.1 timing characteristics 8.2 timing definition 9.0 power consumption 10.0 power on/off sequence 11.0 mechanical characteristics 12.0 national test lab requirement engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 2/31
ii record of revision updated by establishment of the new company as "international display technology". oem i-97c-02 january 15,2002 based on internal spec. ec f79475 as of january 31,2001. to avoid using "inch" indication. to update handling precautions. to update absolute maximum ratings. to update interface signal connector. to update interface signal description. to update interface signal electrical characteristics. 1,5,6,7 4 8 11 12,13 14,15,16,17,18 oem97c-02 may 14,2001 first edition for customer. ITUX97C is based on itux97s. the difference is cable length only. cable length : 125mm all oem97c-01 january 10,2001 summary page document revision date engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 3/31
1.0 handling precautions 1) since front polarizer is easily damaged, pay attention not to scratch it. 2) be sure to turn off power supply when inserting or disconnecting from input connector. 3) wipe off water drop immediately. long contact with water may cause discoloration or spots. 4) when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. 5) since the panel is made of glass, it may break or crack if dropped or bumped on hard surface. 6) since cmos lsi is used in this module, take care of static electricity and insure human earth when handling. 7) do not open nor modify the module assembly. 8) do not press the reflector sheet at the back of the module to any directions. 9) do not stick the adhesive tape on the reflector sheet at the back of the lcd module. 10) in case if a module has to be put back into the packing container slot after once it was taken out from the container, do not press the center of the cfl reflector edge. instead, press at the far ends of the cfl reflector edge softly. otherwise the tft module may be damaged. 11) at the insertion or removal of the signal interface connector, be sure not to rotate nor tilt the interface connector of the tft module. 12) after installation of the tft module into an enclosure ( notebook pc bezel, for example), do not twist nor bent the tft module even momentary. at designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the tft module from outside. otherwise the tft module may be damaged. 13) the fluorescent lamp in the liquid crystal display (lcd) contains mercury. do not put it in trash that is disposed of in landfills. dispose of it as required by local ordinances or regulations. 14)small amount of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source (2.11, iec60950 or ul1950), or be applied exemption conditions of flammability requirements (4.4.3.3, iec60950 or ul1950) in an end product. 15)the lcd module is designed so that the cfl in it is supplied by limited current circuit (2.4, iec60950 or ul1950). do not connect the cfl in hazardous voltage circuit. the information contained herein may be changed without prior notice. it is therefore advisable to contact international display technology before proceeding with the design of equipment incorporating this product. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by international display technology for any infringements of patents or other right of the third partied which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of international display technology or others. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 4/31
2.0 general description this specification applies to the type 15.0 color tft/lcd module 'ITUX97C'. this module is designed for a display unit of notebook style personal computer. the screen format and electrical interface are intended to support the uxga(1600(h) x 1200(v)) screen. support color is native 262k colors(rgb 6-bit data driver). all input signals are lvds(low voltage differential signaling) interface compatible. this module does not contain an inverter card for backlight. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 5/31
2.1 characteristics the following items are characteristics summary on the table under 25 degree c condition: 0 to +50 -20 to +60 temperature range [degree c] operating storage (shipping) 8 pairs lvds(even/odd r/g/b data(6bit), 3sync signals, clock) electrical interface 5.1typ.6.1max,(w/o inverter loss) 6.8typ.8.1max,(w/o inverter loss) typical power consumption [watt] (vdd line + vcfl line) design point 1:(icfl=3.5ma) design point 2:(icfl=6.5ma) 2.7typ.,(w/o inverter loss) 4.4typ.,(w/o inverter loss) lamp power consumption [watt] (vcfl line) design point 1:(icfl=3.5ma) design point 2:(icfl=6.5ma) 2.4 typ.,3.4max. power consumption [wa tt](vdd line) +3.3 typ. nominal input voltage vdd [volt] 30typ.,50 max. optical rise time/fall time [msec] 200 : 1 typ. contrast ratio 90 typ(center) 85 typ(5 points average) 150 typ(center)140 typ(5 points average) white luminance [cd/m 2 ] design point 1:(icfl=3.5ma) design point 2:(icfl=6.5ma) native 262k colors(rgb 6-bit data driver) support color normally white display mode 317.3(w) x 242.0(h) x 6.7(d) typ.7.0(d)max. physical size [mm] 650typ. 685max. weight [grams] r,g,b vertical stripe pixel arrangement 0.1905(per one triad) x 0.1905 pixel pitch [mm] 304.8(h) x 228.6(v) active area [mm] 1600(x3) x 1200 pixels h x v 381(15.0") screen diagonal [mm] specifications characteristics items engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 6/31
2.2 functional block diagram the following diagram shows the functional block of the type 15.0 color tft/lcd module. the first lvds port transmits even pixels while the second lvds port transmits odd pixels. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 7/31 j a e f i - x b 3 0 s - h f 1 0 ( 3 0 p i n ) x-driver tft array/cell 6bit color data for r/g/b dtclk(even/odd) dsptmg hsync vsync vdd lcd controller lcd drive card backlight unit 1600(r/g/b) x 1200 gnd dc-dc converter ref circuit (even/odd) < 8 pairs lvds > even pixcel odd pixcel dual lvds receiver lcd-drive connector y-driver g/a lamp connector jst bhsr-02vs-1 (2pin)
3.0 absolute maximum ratings absolute maximum ratings of the module is as follows : rectangle wave g ms 50 18 shock g hz 1.5 10-200 vibration note 1 %rh 95 5 hst storage relative humidity note 1 deg.c +60 -20 tst storage temperature note 1 %rh 95 8 hop operating relative humidity note 1 deg.c +50 0 top operating temperature ma 20 - icflp cfl peak inrush current mams 7 - icfl cfl current note 2 vrms +1,600 - vs cfl ignition voltage v vdd+0.3 -0.3 vin input signal voltage v +4.0 -0.3 vdd logic/lcd drive voltage conditions unit max min s y mbol item note 1 : maximum wet-bulb should be 39 degree c and no condensation . note 2 : duration : 50msec max. ta=0 degree c engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 8/31
4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 degree c condition : - 150typ. center 140typ. 5 points average white luminance (cd/m 2 ) icfl 6.5 ma - 0.329 white y - 0.313 white x - 0.132 blue y - 0.149 blue x - 0.544 green y - 0.312 green x (cie) - 0.332 red y chromaticity - 0.569 red x color 50max 30 falling (ms) 50max 30 rising response time - 200 contrast ratio - - 15 30 vertical (upper) k 10 (lower) k:contrast ratio - - 40 40 horizontal (right) k 10 (left) viewing angle (degrees) note typ. specification conditions item engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 9/31
5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. fi-x30m mating type / part number fi-xb30s-hf10 type / part number jae manufacturer for signal connector connector name / designation sm02b-bhss-1 mating type / part number bhsr-02vs-1 type / part number jst manufacturer for lamp connector connector name / designation engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 10/31
5.2 interface signal connector fg ( gnd ) 32 rein2+ 16 roclkin+ 31 rein2- 15 roclkin- 30 gnd 14 gnd 29 rein1+ 13 roin2+ 28 rein1- 12 roin2- 27 gnd 11 gnd 26 rein0+ 10 roin1+ 25 rein0- 9 roin1- 24 data eedid ( note 2 , 4 ) 8 gnd 23 clk eedid ( note 2 , 4 ) 7 roin0+ 22 reserved ( note 1 ) 6 roin0- 21 v eedid ( note 2 , 3 ) 5 gnd 20 vdd 4 reclkin+ 19 vdd 3 reclkin- 18 gnd 2 gnd 17 fg ( gnd ) 1 s i g n a l n a m e pin # s i g n a l n a m e pin # note: 1. 'reserved' pins are not allowed to connect any other line. 2. this lcd module complies with "vesa enhanced extended display identification data standard release a, revision 1" and supports "eedid version 1.3". 3. v eedid power source shall be the limited current circuit which has not exceeding 1a. (reference document : "enhanced display data channel (e-ddc tm ) proposed standard", vesa) 4. both clk eedid line and data eedid line are pulled up with 10k ohm resistor to v eedid power source line at lcd panel, respectively. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 11/31
5.3 interface signal description the module uses a pair of lvds receiver. lvds is a differential signal technology for lcd interface and high speed data transfer device. transmitter shall be a negative edge sampling type. frame ground fg 32 positive lvds differential clock input (odd) roclkin+ 31 negative lvds differential clock input (odd) roclkin- 30 ground gnd 29 positive lvds differential data input (odd b2-b5) roin2+ 28 negative lvds differential data input (odd b2-b5) roin2- 27 ground gnd 26 positive lvds differential data input (odd g1-g5, b0-b1) roin1+ 25 negative lvds differential data input (odd g1-g5, b0-b1) roin1- 24 ground gnd 23 positive lvds differential data input (odd r0-r5, g0) roin0+ 22 negative lvds differential data input (odd r0-r5, g0) roin0- 21 ground gnd 20 positive lvds differential clock input (even) reclkin+ 19 negative lvds differential clock input (even) reclkin- 18 ground gnd 17 positive lvds differential data input (even b2-b5, hsync, vsync, dsptmg) rein2+ 16 negative lvds differential data input (even b2-b5, hsync, vsync, dsptmg) rein2- 15 ground gnd 14 positive lvds differential data input (even g1-g5, b0-b1) rein1+ 13 negative lvds differential data input (even g1-g5, b0-b1) rein1- 12 ground gnd 11 positive lvds differential data input (even r0-r5, g0) rein0+ 10 negative lvds differential data input (even r0-r5, g0) rein0- 9 eedid data data eedid 8 eedid clock clk eedid 7 reserved reserved 6 eedid 3.3v power supply v eedid 5 +3.3v power supply vdd 4 +3.3v power supply vdd 3 ground gnd 2 frame ground fg 1 description signal name pin # note: 1. input signals of odd and even clock shall be the same timing. 2. the module uses a 100ohm resistor between positive and negative data lines of each receiver input. 3. even: first pixel , odd: second pixel engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 12/31
eedid data data eedid eedid clock clk edid eedid 3.3v power supply v eedid ground gnd power supply vdd horizontal sync: this signal is synchronized with dtclk. both active high/low signals are acceptable. hsync (h-s) vertical sync: this signal is synchronized with dtclk. both active high/low signals are acceptable. vsync (v-s) when the signal is high, the pixel data shall be valid to be displayed. +dsptmg (dsp) the signal is used to strobe the pixel +data and the +dsptmg (even/odd) data clock: the typical frequency is 81mhz. dtclk blue-pixel data: each blue pixel's brightness data consists of these 6 bits pixel data. (even/odd) blue data 0 (lsb) +blue 0 (eb0/ob0) blue data 1 +blue 1 (eb1/ob1) blue data 2 +blue 2 (eb2/ob2) blue data 3 +blue 3 (eb3/ob3) blue data 4 +blue 4 (eb4/ob4) blue data 5 (msb) +blue 5 (eb5/ob5) green-pixel data: each green pixel's brightness data consists of these 6 bits pixel data. (even/odd) green data 0 (lsb) +green 0 (eg0/og0) green data 1 +green 1 (eg1/og1) green data 2 +green 2 (eg2/og2) green data 3 +green 3 (eg3/og3) green data 4 +green 4 (eg4/og4) green data 5 (msb) +green 5 (eg5/og5) red-pixel data: each red pixel's brightness data consists of these 6 bits pixel data. (even/odd) red data 0 (lsb) +red 0 (er0/or0) red data 1 +red 1 (er1/or1) red data 2 +red 2 (er2/or2) red data 3 +red 3 (er3/or3) red data 4 +red 4 (er4/or4) red data 5 (msb) +red 5 (er5/or5) description signal name note: output signals except v eedid ,clk eedid and data eedid from any system shall be hi-z state when vdd is off. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 13/31
5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver electrical characteristics [mv] +50 -50 vcm common mode voltage offset [v] | vid | 2.4 - 2 | vid | 0.825+ 2 vic common mode input voltage [mv] 600 100 |vid| magnitude differential input voltage [mv] -100 vtl differential input low threshold [mv] +100 vth differential input high threshold unit max min symbol parameter note: input signals shall be low or hi-z state when vdd is off. voltage definitions engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 14/31
switching characteristics ps/clk 20 tcjavg cycle modulation rate(note) ps 600 thd data hold time (uxga fpt) fc = 66.4mhz, jitter < 50ps ps 500 thd data hold time (uxga) ps 600 tsu data setup time (uxga fpt) fc = 81.0mhz, jitter < 50ps ps 500 tsu data setup time (uxga) ns 16.4 15.1 14.5 tc cycle time (uxga fpt) ns 13.3 12.3 12.0 tc cycle time (uxga) mhz 69.0 66.4 61.0 fc clock frequency (uxga fpt) mhz 83.0 81.0 75.0 fc clock frequency (uxga) conditions unit max typ min symbol parameter note: this specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. this specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps. timing definition (even) engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 15/31
timing definition (odd) engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 16/31
timing definition(detail a) engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 17/31
5.4.2 lvds receiver internal circuit below figure shows the internal block diagram of the lvds receiver. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 18/31
5.5 signal for lamp connector lamp low voltage 2 lamp high voltage 1 signal name pin # engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 19/31
6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format image. even and odd pair of rgb data are sampled at a time . r g b r g b r g b r g b r g b r g b r g b r g b even odd even odd 0 1 1599 1st line 1200th line 1598 engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 20/31
7.0 parameter guide line for cfl inverter (ta=25 deg.c) note 2 w - 4.4 2.7 - cfl power consumption(pcfl) (ta=25 deg.c) note 2 vrms - 645 745 - cfl voltage (reference)(vcfl) (ta= 0 deg.c) note 3 vrms - - - 1,450 cfl ignition voltage(vs) (ta=25 deg.c) note 1 khz 60 - - 40 cfl frequency(fcfl) (ta=25 deg.c) marms 7.0 6.5 3.5 3.0 cfl current(icfl) (ta=25 deg.c) cd/m 2 - - 150 140 90 85 - - white luminance (center) (5 points average) condition units max dp-2 dp-1 min parameter note 1: cfl discharge frequency should be carefully determined to avoid interference between inverter and tft lcd. note 2: calculated value for reference (icfl x vcfl = pcfl). note 3: cfl inverter should be able to give out a power that has a generating capacity of over 1,450 voltage. lamp units need 1,450 voltage minimum for ignition. note 4: dp-1 and dp-2 are recommended design points. *1 all of characteristics listed are measured under the condition using the test inverter. *2 in case of using an inverter other than listed, it is recommended to check the inverter carefully. sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 in designing an inverter, it is suggested to check safety circuit very carefully. impedance of cfl, for instance, becomes more than 1 [m ohm] when cfl is damaged. *4 generally, cfl has some amount of delay time after applying kick-off voltage. it is recommended to keep on applying kick-off voltage for 1 [sec] until discharge. *5 cfl discharge frequency must be carefully chosen so as not to produce interfering noise stripes on the screen. *6 reducing cfl current increases cfl discharge voltage and generally increases cfl discharge frequency. so all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. *7 it should be employed the inverter which has 'duty dimming', if icfl is less than 4ma. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 21/31
the following chart is cfl current versus the luminance for your reference. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 22/31
8.0 interface timings basically, interface timings described here is not actual input timing of lcd module but output timing of sn75lvds86(texas instruments) or equivalent. 8.1 timing characteristics (vesa uxga mode) [dots] 1600 n data even/odd +data [usec] 9.877 thd display +dsptmg [tck] 32 8 thf h-front porch [tck] 511 152 8 thb h-back porch [tck] 255 96 8 tha [usec] 1.185 tha h-active level [tck] 2047 1080 1024 nh [usec] 13.33 th [khz] 75.0 fh scan rate +h-sync [lines] 1200 m v-line +dsptmg [lines] 125 1 1 nvf v-front porch [lines] 125 46 6 nvb v-back porch [lines] 63 3 1 nva [us] 839.8 40.0 13.33 tva v-active level [lines] 2046 1250 1208 nv [ms] 16.67 tv [hz] 60.0 fv frame rate +v-sync [ns] 13.3 12.3 12.0 tck [mhz] 83.0 81.0 75.0 fdck freqency dtclk unit max. typ. min. symbol item signal note:both positive hsync and positive vsync polarity is recommended. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 23/31
(vesa uxga fpt mode) [dots] 1600 n data even/odd +data [usec] 12.053 thd display +dsptmg [tck] 48 8 thf h-front porch [tck] 511 56 8 thb h-back porch [tck] 255 8 8 tha [usec] 0.121 tha h-active level [tck] 1023 912 873 nh [usec] 13.74 th [khz] 73.0 fh scan rate +h-sync [lines] 1200 m v-line +dsptmg [lines] 125 12 3 nvf v-front porch [lines] 125 1 1 nvb v-back porch [lines] 63 1 1 nva [us] 13.7 13.7 tva v-active level [lines] 2046 1214 1208 nv [ms] 16.67 tv [hz] 60.0 fv frame rate +v-sync [ns] 16.4 15.1 14.5 tck [mhz] 69.0 66.4 61.0 fdck freqency dtclk unit max. typ. min. symbol item signal note:both positive hsync and positive vsync polarity is recommended. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 24/31
8.2 timing definition basically, dor count described here is not actual input dot count of lcd module. (vesa uxga mode) typical vertical timing table 0.613 ms (46 lines) 0.040 ms (3 lines) 16.667 ms (1250 lines) 0.013 ms (1 line) 16.000 ms (1200 lines) 0.667 ms (50 lines) 1600 x 1200 at 60hz (h line rate : 13.3 us) tvb vsync back porch tva vsync width tv,nv frame time tvf vsync front porch m active field tvblk vertical blanking support mode typical horizontal timing table 1.877 us (304 dots) 1.185 us (192 dots) 13.333 us (2160 dots) 0.395 us (64 dots) 9.877 us (1600 dots) 3.457 us (560 dots) 1600 x 1200 dotclock : 162.000 mhz (81.000mhz x2) thb hsync back porch tha hsync width th,nh h line time thf hsync front porch thd active field thblk horizontal blanking support mode (vesa uxga fpt mode) typical vertical timing table 0.014 ms (1 line) 0.014 ms (1 line) 16.632 ms (1214 lines) 0.164 ms (12 line) 16.440 ms (1200 lines) 0.192 ms (14 lines) 1600 x 1200 at 60hz (h line rate : 13.7 us) tvb vsync back porch tva vsync width tv,nv frame time tvf vsync front porch m active field tvblk vertical blanking support mode typical horizontal timing table 0.844 us (112 dots) 0.121 us (16 dots) 13.740 us (1824 dots) 0.723 us (96 dots) 12.053 us (1600 dots) 1.687 us (224 dots) 1600 x 1200 dotclock : 132.75 mhz (66.375mhz x2) thb hsync back porch tha hsync width th,nh h line time thf hsync front porch thd active field thblk horizontal blanking support mode engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 25/31
tvblk m tvf tva tvb tv dsptmg -vsync +vsync thblk thd thf tha thb th dsptmg -hsync +hsync 0 2 4 n-4 n-2 video(even) video(odd) video(even) video(odd) dtclk 1 3 5 n-3 n-1 tck engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 26/31
9.0 power consumption input power specifications are as follows; [mvp-p] 100 allowable logic/lcd drive ripple noise vddns [mvp-p] 100 allowable logic/lcd drive ripple voltage vddrp all black pattern, vdd=3.3[v] [ma] 730 vdd current idd max pattern, vdd=3.0[v] [ma] 940 vdd current idd all black pattern, vdd=3.3[v] [w] 2.4 vdd power pdd max. pattern, vdd=3.6[v] [w] 3.4 vdd power pdd load capacitance 68uf [v] 3.6 3.3 3.0 logic/lcd drive voltage vdd condition units max typ min parameter symbol note: max pattern:2 dot vertical sub-pixel stripe. engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 27/31
10.0 power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. 90% 10% 10% 10% 90% 10ms max. 0 min. 0 v 0 v vdd signals 180ms min. 0 min. 10% 10% 150ms min. 100ms min. 20ms min. lamp 90% 90% on (recommended). engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 28/31
11.0 mechanical characteristics engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 29/31
engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 30/31
12.0 national test lab requirement the display module is authorized to apply the ul recognized mark. conditions of acceptability this component has been judged on the basis of the required spacings in the standard for safety of information technology equipment, including electrical business equipment, can/csa c22.2 no.950-95 *ul 1950, third edition, including revisions through revision date march 1,1998, which are based on the fourth amendment to iec 950, second edition, which would cover the component itself if submitted for listing. cf lamp circuit for this model should be supplied from limited current circuit. the units are supplied by limited power sources. the terminals and connectors are suitable for factory wiring only. the terminals and connectors have not been evaluated for field wiring. a suitable electrical and fire enclosure shall be provided. ****** end of page ****** engineering specification (c) copyright international display technology 2002 all rights reserved. january 15,2002 oem i-97c-02 31/31

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